Finished Part I, moved part 2 relavent files to own folder.
This commit is contained in:
17
Part2/A4/05_basic_int/cpu/idt.c
Executable file
17
Part2/A4/05_basic_int/cpu/idt.c
Executable file
@@ -0,0 +1,17 @@
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#include "idt.h"
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#include "../kernel/util.h"
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void set_idt_gate(int n, u32 handler) {
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idt[n].low_offset = low_16(handler);
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idt[n].sel = KERNEL_CS;
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idt[n].always0 = 0;
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idt[n].flags = 0x8E;
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idt[n].high_offset = high_16(handler);
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}
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void set_idt() {
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idt_reg.base = (u32) &idt;
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idt_reg.limit = IDT_ENTRIES * sizeof(idt_gate_t) - 1;
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/* Don't make the mistake of loading &idt -- always load &idt_reg */
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__asm__ __volatile__("lidtl (%0)" : : "r" (&idt_reg));
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}
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39
Part2/A4/05_basic_int/cpu/idt.h
Executable file
39
Part2/A4/05_basic_int/cpu/idt.h
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@@ -0,0 +1,39 @@
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#ifndef IDT_H
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#define IDT_H
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#include "types.h"
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/* Segment selectors */
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#define KERNEL_CS 0x08
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/* How every interrupt gate (handler) is defined */
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typedef struct {
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u16 low_offset; /* Lower 16 bits of handler function address */
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u16 sel; /* Kernel segment selector */
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u8 always0;
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/* First byte
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* Bit 7: "Interrupt is present"
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* Bits 6-5: Privilege level of caller (0=kernel..3=user)
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* Bit 4: Set to 0 for interrupt gates
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* Bits 3-0: bits 1110 = decimal 14 = "32 bit interrupt gate" */
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u8 flags;
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u16 high_offset; /* Higher 16 bits of handler function address */
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} __attribute__((packed)) idt_gate_t ;
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/* A pointer to the array of interrupt handlers.
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* Assembly instruction 'lidt' will read it */
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typedef struct {
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u16 limit;
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u32 base;
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} __attribute__((packed)) idt_register_t;
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#define IDT_ENTRIES 256
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idt_gate_t idt[IDT_ENTRIES];
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idt_register_t idt_reg;
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/* Functions implemented in idt.c */
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void set_idt_gate(int n, u32 handler);
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void set_idt();
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#endif
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287
Part2/A4/05_basic_int/cpu/interrupt.asm
Executable file
287
Part2/A4/05_basic_int/cpu/interrupt.asm
Executable file
@@ -0,0 +1,287 @@
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; Defined in isr.c
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[extern isr_handler]
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; Common ISR code
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isr_common_stub:
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; 1. Save CPU state
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pusha ; Pushes edi,esi,ebp,esp,ebx,edx,ecx,eax
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mov ax, ds ; Lower 16-bits of eax = ds.
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push eax ; save the data segment descriptor
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mov ax, 0x10 ; kernel data segment descriptor
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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; 2. Call C handler
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call isr_handler
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; 3. Restore state
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pop eax
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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popa
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add esp, 8 ; Cleans up the pushed error code and pushed ISR number
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sti
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iret ; pops 5 things at once: CS, EIP, EFLAGS, SS, and ESP
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; We don't get information about which interrupt was caller
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; when the handler is run, so we will need to have a different handler
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; for every interrupt.
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; Furthermore, some interrupts push an error code onto the stack but others
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; don't, so we will push a dummy error code for those which don't, so that
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; we have a consistent stack for all of them.
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; First make the ISRs global
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global isr0
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global isr1
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global isr2
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global isr3
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global isr4
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global isr5
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global isr6
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global isr7
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global isr8
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global isr9
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global isr10
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global isr11
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global isr12
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global isr13
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global isr14
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global isr15
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global isr16
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global isr17
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global isr18
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global isr19
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global isr20
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global isr21
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global isr22
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global isr23
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global isr24
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global isr25
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global isr26
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global isr27
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global isr28
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global isr29
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global isr30
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global isr31
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; 0: Divide By Zero Exception
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isr0:
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cli
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push byte 0
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push byte 0
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jmp isr_common_stub
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; 1: Debug Exception
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isr1:
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cli
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push byte 0
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push byte 1
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jmp isr_common_stub
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; 2: Non Maskable Interrupt Exception
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isr2:
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cli
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push byte 0
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push byte 2
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jmp isr_common_stub
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; 3: Int 3 Exception
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isr3:
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cli
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push byte 0
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push byte 3
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jmp isr_common_stub
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; 4: INTO Exception
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isr4:
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cli
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push byte 0
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push byte 4
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jmp isr_common_stub
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; 5: Out of Bounds Exception
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isr5:
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cli
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push byte 0
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push byte 5
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jmp isr_common_stub
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; 6: Invalid Opcode Exception
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isr6:
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cli
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push byte 0
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push byte 6
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jmp isr_common_stub
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; 7: Coprocessor Not Available Exception
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isr7:
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cli
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push byte 0
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push byte 7
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jmp isr_common_stub
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; 8: Double Fault Exception (With Error Code!)
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isr8:
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cli
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push byte 8
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jmp isr_common_stub
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; 9: Coprocessor Segment Overrun Exception
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isr9:
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cli
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push byte 0
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push byte 9
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jmp isr_common_stub
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; 10: Bad TSS Exception (With Error Code!)
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isr10:
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cli
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push byte 10
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jmp isr_common_stub
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; 11: Segment Not Present Exception (With Error Code!)
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isr11:
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cli
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push byte 11
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jmp isr_common_stub
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; 12: Stack Fault Exception (With Error Code!)
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isr12:
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cli
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push byte 12
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jmp isr_common_stub
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; 13: General Protection Fault Exception (With Error Code!)
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isr13:
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cli
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push byte 13
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jmp isr_common_stub
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; 14: Page Fault Exception (With Error Code!)
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isr14:
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cli
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push byte 14
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jmp isr_common_stub
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; 15: Reserved Exception
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isr15:
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cli
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push byte 0
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push byte 15
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jmp isr_common_stub
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; 16: Floating Point Exception
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isr16:
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cli
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push byte 0
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push byte 16
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jmp isr_common_stub
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; 17: Alignment Check Exception
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isr17:
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cli
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push byte 0
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push byte 17
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jmp isr_common_stub
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; 18: Machine Check Exception
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isr18:
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cli
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push byte 0
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push byte 18
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jmp isr_common_stub
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; 19: Reserved
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isr19:
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cli
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push byte 0
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push byte 19
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jmp isr_common_stub
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; 20: Reserved
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isr20:
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cli
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push byte 0
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push byte 20
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jmp isr_common_stub
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; 21: Reserved
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isr21:
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cli
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push byte 0
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push byte 21
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jmp isr_common_stub
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; 22: Reserved
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isr22:
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cli
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push byte 0
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push byte 22
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jmp isr_common_stub
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; 23: Reserved
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isr23:
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cli
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push byte 0
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push byte 23
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jmp isr_common_stub
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; 24: Reserved
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isr24:
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cli
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push byte 0
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push byte 24
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jmp isr_common_stub
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; 25: Reserved
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isr25:
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cli
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push byte 0
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push byte 25
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jmp isr_common_stub
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; 26: Reserved
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isr26:
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cli
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push byte 0
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push byte 26
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jmp isr_common_stub
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; 27: Reserved
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isr27:
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cli
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push byte 0
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push byte 27
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jmp isr_common_stub
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; 28: Reserved
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isr28:
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cli
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push byte 0
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push byte 28
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jmp isr_common_stub
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; 29: Reserved
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isr29:
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cli
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push byte 0
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push byte 29
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jmp isr_common_stub
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; 30: Reserved
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isr30:
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cli
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push byte 0
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push byte 30
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jmp isr_common_stub
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; 31: Reserved
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isr31:
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cli
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push byte 0
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push byte 31
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jmp isr_common_stub
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92
Part2/A4/05_basic_int/cpu/isr.c
Executable file
92
Part2/A4/05_basic_int/cpu/isr.c
Executable file
@@ -0,0 +1,92 @@
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#include "isr.h"
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#include "idt.h"
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#include "../drivers/screen.h"
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#include "../kernel/util.h"
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/* Can't do this with a loop because we need the address
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* of the function names */
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void isr_install() {
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set_idt_gate(0, (u32)isr0);
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set_idt_gate(1, (u32)isr1);
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set_idt_gate(2, (u32)isr2);
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set_idt_gate(3, (u32)isr3);
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set_idt_gate(4, (u32)isr4);
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set_idt_gate(5, (u32)isr5);
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set_idt_gate(6, (u32)isr6);
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set_idt_gate(7, (u32)isr7);
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set_idt_gate(8, (u32)isr8);
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set_idt_gate(9, (u32)isr9);
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set_idt_gate(10, (u32)isr10);
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set_idt_gate(11, (u32)isr11);
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set_idt_gate(12, (u32)isr12);
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set_idt_gate(13, (u32)isr13);
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set_idt_gate(14, (u32)isr14);
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set_idt_gate(15, (u32)isr15);
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set_idt_gate(16, (u32)isr16);
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set_idt_gate(17, (u32)isr17);
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set_idt_gate(18, (u32)isr18);
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set_idt_gate(19, (u32)isr19);
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set_idt_gate(20, (u32)isr20);
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set_idt_gate(21, (u32)isr21);
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set_idt_gate(22, (u32)isr22);
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set_idt_gate(23, (u32)isr23);
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set_idt_gate(24, (u32)isr24);
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set_idt_gate(25, (u32)isr25);
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set_idt_gate(26, (u32)isr26);
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set_idt_gate(27, (u32)isr27);
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set_idt_gate(28, (u32)isr28);
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set_idt_gate(29, (u32)isr29);
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set_idt_gate(30, (u32)isr30);
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set_idt_gate(31, (u32)isr31);
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set_idt(); // Load with ASM
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}
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/* To print the message which defines every exception */
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char *exception_messages[] = {
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"Division By Zero",
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"Debug",
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"Non Maskable Interrupt",
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"Breakpoint",
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"Into Detected Overflow",
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"Out of Bounds",
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"Invalid Opcode",
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"No Coprocessor",
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"Double Fault",
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"Coprocessor Segment Overrun",
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"Bad TSS",
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"Segment Not Present",
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"Stack Fault",
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"General Protection Fault",
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"Page Fault",
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"Unknown Interrupt",
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"Coprocessor Fault",
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"Alignment Check",
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"Machine Check",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved"
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};
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void isr_handler(registers_t r) {
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kprint("received interrupt: ");
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char s[3];
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int_to_ascii(r.int_no, s);
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kprint(s);
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kprint("\n");
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kprint(exception_messages[r.int_no]);
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kprint("\n");
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}
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51
Part2/A4/05_basic_int/cpu/isr.h
Executable file
51
Part2/A4/05_basic_int/cpu/isr.h
Executable file
@@ -0,0 +1,51 @@
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#ifndef ISR_H
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#define ISR_H
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#include "types.h"
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/* ISRs reserved for CPU exceptions */
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extern void isr0();
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extern void isr1();
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extern void isr2();
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extern void isr3();
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extern void isr4();
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extern void isr5();
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extern void isr6();
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extern void isr7();
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extern void isr8();
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extern void isr9();
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extern void isr10();
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extern void isr11();
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extern void isr12();
|
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extern void isr13();
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extern void isr14();
|
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extern void isr15();
|
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extern void isr16();
|
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extern void isr17();
|
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extern void isr18();
|
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extern void isr19();
|
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extern void isr20();
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extern void isr21();
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extern void isr22();
|
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extern void isr23();
|
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extern void isr24();
|
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extern void isr25();
|
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extern void isr26();
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extern void isr27();
|
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extern void isr28();
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extern void isr29();
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extern void isr30();
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extern void isr31();
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/* Struct which aggregates many registers */
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typedef struct {
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u32 ds; /* Data segment selector */
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u32 edi, esi, ebp, esp, ebx, edx, ecx, eax; /* Pushed by pusha. */
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u32 int_no, err_code; /* Interrupt number and error code (if applicable) */
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u32 eip, cs, eflags, useresp, ss; /* Pushed by the processor automatically */
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} registers_t;
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void isr_install();
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void isr_handler(registers_t r);
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|
||||
#endif
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16
Part2/A4/05_basic_int/cpu/types.h
Executable file
16
Part2/A4/05_basic_int/cpu/types.h
Executable file
@@ -0,0 +1,16 @@
|
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#ifndef TYPES_H
|
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#define TYPES_H
|
||||
|
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/* Instead of using 'chars' to allocate non-character bytes,
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* we will use these new type with no semantic meaning */
|
||||
typedef unsigned int u32;
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||||
typedef int s32;
|
||||
typedef unsigned short u16;
|
||||
typedef short s16;
|
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typedef unsigned char u8;
|
||||
typedef char s8;
|
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|
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#define low_16(address) (u16)((address) & 0xFFFF)
|
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#define high_16(address) (u16)(((address) >> 16) & 0xFFFF)
|
||||
|
||||
#endif
|
||||
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Block a user